One significant advantage of using a single-chip solution is the minimal number of software blocks that need to be integrated in the critical data path of the packet flow, thereby reducing software-related overhead and sustaining the system performance to meet the multi-gigabit wire-speed demands. Figure 1 below illustrates how the following major software components fit in the management, control and data planes in a unified enterprise LAN infrastructure:

Ensuring that a branch circuit is loaded to less than 50% of its rating is a task made more difficult when the loads exhibit dynamic power consumption. A system may be tested upon installation and be found to have branch circuits operating below 50% rating, and then at some future time of high computational load the system may be operating at greater than 50% rating.

The 3-Mbit Improvement The 3X (3-Mbit) data rate uses eight-phase differential phase-shift keying (8DPSK), which is similar to π/4-DQPSK but allows differential moves to any of the eight possible phase positions. In 8DPSK, the separation between the possible phase positions for each symbol is reduced to 45 deg. (see Figure 2 above).