Lattice has put together an offering based on using two accelerator cores in its FPGAs — one for widely used convolutional neural networks and another for binarized neural nets. The chips span a power consumption range from a milliwatt to a watt with package sizes as small as 5.5 mm2 and volume prices ranging from $1 to $10.
Some users might be familiar with the WP pin in parallel Flash devices, which has a simple Write Protect function. The function of the WP pin in serial NOR Flash devices is different: it protects the register settings that configure the Program/Erase protection of blocks and sectors via the BP and SEC register bits. Once the BP and SEC settings are made and the WP pin is asserted (WP=Low), no change to the BP and SEC settings may be made without pulling the WP pin High.
Deep neural networks are essentially a new way of computing. Instead of writing a program to run on a processor that spits out data, you stream data through an algorithmic model that filters out results in what’s called inference processing.