The value for this bandwidth has a direct impact on the performance of the PLL. If the value of the loop bandwidth is large, the loop filter can pass a wide range of frequencies for the error signal. A wide loop bandwidth will thus allow the PLL to track out large frequency errors. However, it will also pass a wider portion of the noise spectrum. The end result is a noisy control signal for the NCO and that translates into phase jitter on the locally generated signal y(t) .

Although multiple ports can transfer simultaneously to each other and to different memory areas, only one transfer can take place at a time through each memory/slave interface. Therefore, while the SCR eliminates the bus as a data bottleneck, care must be taken not to create a new bottleneck at the external memory interface (EMIF) to system memory. That potential problem can be minimized, if not eliminated, by storing CPPI buffer address descriptors in on-chip SRAM instead of in the main memory. The CPU can then access the on-chip SRAM for descriptors, instead of clogging the EMIF with stores and fetches. The EMIF is thus freed to handle DMAs much more efficiently.

On to Part 2 That wraps our discussion on Layers 5 to 7 of the OSI stack. In Part 2, we'll continue the discussion by examining Layer 4 (transport), Layer 3 (network), Layer 2 (data link), and layer 1 (Physical). We'll also discuss some non-model but very important pieces, especially for embedded devices; those pieces include network-aware bootloaders and other functions.